This invention relates to integrated-circuit memory arrays, including electrically-programmable, read-only-memory (EPROM) arrays, and to a common-line connection for integrated-circuit memories having segmented arrays and distributed circuitry for programming and reading the individual cells of those memories.
In particular, this invention relates to a connection providing a common path for programming logic signals, for programming voltages, for data signal transmission, and for sense amplifier bias voltage in an integrated memory device.
An EPROM array is one example of an integrated circuit in which the circuit and method of this invention may be used. EPROM arrays include floating-gate memory cells arranged in rows and columns. The floating gate of a programmed memory cell is charged with electrons, and the electrons in turn render the source-drain path under the charged floating gate nonconductive when a chosen row-line select voltage is applied to the control gate. The nonconductive state is read as a "zero" bit. The floating gate of a non-programmed cell is neutrally charged such that the source-drain path under the non-programmed floating gate is conductive when the same chosen row-line select voltage is applied to the control gate. The conductive state is read as a "one" bit.
Each column and row of an EPROM array may contain thousands of cells. The sources of each cell in a column are connected to a virtual-ground line (source-column line). The drains of each cell in a column are connected to a separate bitline (drain-column line). The control gates of each cell in a row are connected to a wordline.
Programmable memories commonly have read circuitry and program circuitry joining at a common node and, in some cases, sharing some devices. The term "read circuitry" as used herein refers to components that are implemented to determine the state of a memory cell. The term "program circuitry" as used herein refers to components that program or alter the state of a memory cell. An example of transistors and interconnect components that are used by both read and program circuitry is the decoding circuitry used to select columns in an EPROM.
Prior-art circuitry includes switching transistors that select which column to either program or read in response to a signal from a decoder. In such prior-art circuitry, a program enable input signal determines which block of circuitry, the program circuitry or the read circuitry, is activated. The two circuitry blocks are joined by a common node having the function of either connecting the read circuitry to the column or forcing programming potentials onto the column.
There is a need for reduction in the chip area required to perform read and programming functions, especially where signals for the read and programming circuits are distributed at remote locations on the chip.